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DATA SHEET
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
V850/SA1 32-/16-BIT SINGLE-CHIP MICROCONTROLLER
TM
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit singlechip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller. In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1 includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions, all of which are instructions suited to digital servo control applications. As a real-time control system, this device provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS). Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V850/SA1 User's Manual Hardware: U12768E TM U10243E V850 Family User's Manual Architecture:
FEATURES
{ Number of instructions: 74 { Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX)) 50 ns (@ 20 MHz operation with main system clock (fXX)) 30.5 s (@ 32.768 kHz operation with subsystem clock (fXT)) { General-purpose registers: 32 bits x 32 registers { Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { Memory space: 16 MB linear address space Memory block allocation function: 2 MB per block { External bus interface: 16-bit data bus Address bus: Separate output enabled { Internal memory Mask ROM: 64 KB (PD703014A, 703014AY) 128 KB (PD703015A, 703015AY) 256 KB (PD703017A, 703017AY) RAM: 4 KB (PD703014A, 703014AY, 703015A, 703015AY) 8 KB (PD703017A, 703017AY)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
{ Interrupts and exception External: 8, internal: 23, exception: 1 { I/O lines Total: 85 { Timer/counters 16-bit timer: 8-bit timer: 2 channels 4 channels
{ Watch timer: 1 channel { Watchdog timer: 1 channel { Serial interface (SIO) Asynchronous serial interface (UART) Clocked serial interface (CSI) I2C bus interface (PD703014AY, 703015AY, 703017AY) { A/D converter: 12 channels { DMA controller: 3 channels { RTP: 8 bits x 1 channel or 4 bits x 2 channels { Power-saving functions: HALT/IDLE/STOP modes { Packages: 100-pin plastic LQFP (14 x 14) 121-pin plastic FBGA (12 x 12)
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14526EJ2V0DS00 (2nd edition) Date Published September 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
2000
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
APPLICATIONS
{ Low-power portable devices Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine-pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) Internal ROM 64 KB (Mask ROM) 64 KB (Mask ROM) 64 KB (Mask ROM) 64 KB (Mask ROM) 128 KB (Mask ROM) 128 KB (Mask ROM) 128 KB (Mask ROM) 128 KB (Mask ROM) 256 KB (Mask ROM) 256 KB (Mask ROM) 256 KB (Mask ROM) 256 KB (Mask ROM)
PD703014AGC-xxx-8EU PD703014AF1-xxx-EA6 PD703014AYGC-xxx-8EU PD703014AYF1-xxx-EA6 PD703015AGC-xxx-8EU PD703015AF1-xxx-EA6 PD703015AYGC-xxx-8EU PD703015AYF1-xxx-EA6 PD703017AGC-xxx-8EU PD703017AF1-xxx-EA6 PD703017AYGC-xxx-8EU PD703017AYF1-xxx-EA6
Remark
xxx indicates ROM code suffix.
2
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN CONFIGURATION
100-pin plastic LQFP (fine-pitch) (14 x 14)
PD703014AGC-xxx-8EU PD703014AYGC-xxx-8EU PD703015AGC-xxx-8EU PD703015AYGC-xxx-8EU PD703017AGC-xxx-8EU PD703017AYGC-xxx-8EU
P20/SI2 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 P12/SCK0/SCLNote 2 P11/SO0 P10/SI0/SDANote 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
P21/SO2 P22/SCK2 P23/RXD1 P24/TXD1 P25/ASCK1 VDD VSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10 P33/TI11 P34/TO0/A13 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 ICNote 1 P100/RTP0/A5 P101/RTP1/A6 P102/RTP2/A7 P103/RTP3/A8 P104/RTP4/A9 P105/RTP5/A10 P106/RTP6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. Connect the IC pin directly to VSS. 2. Applies to the PD703014AY, 703015AY, and 703017AY only.
P107/RTP7/A12 P110/A1 P111/A2 P112/A3 P113/A4 RESET P114/XT1 XT2 VDD X2 X1 VSS CLKOUT P120/WAIT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3
Data Sheet U14526EJ2V0DS00
3
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
121-pin plastic FBGA (12 x 12)
PD703014AF1-xxx-EA6 PD703014AYF1-xxx-EA6
PD703015AF1-xxx-EA6 PD703015AYF1-xxx-EA6
PD703017AF1-xxx-EA6 PD703017AYF1-xxx-EA6
Top View 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJKLMN
Bottom View
NMLKJHGFEDCBA
Pin Pin Pin Pin Pin Pin Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Number Number Number Number Number Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 P20 P15 VSS P13 P11 P06 P03 P00 P81 P76 P73 P72 AVSS P21 P14 VSS P12 P10 P05 P02 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 P83 P80 P75 AVSS AVSS P71 P22 P23 VSS P24 P07 P04 P01 P82 P77 P74 AVSS P70 AVREF VDD D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 VDD VSS AVDD AVDD AVDD P25 VDD P30 AVDD P64 P65 P26 P27 P33 P63 P61 P62 P31 P32 P36 G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 P60 P56 P57 P34 P37 P35 P55 P53 P54 IC IC
Note Note
K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6
BVDD P104 P105 RESET VDD VSS X2 P90 P120 P93 P96 BVSS BVSS BVSS P106 P111 P113 VDD XT2 X1
M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
VSS VSS P92 P95 P41 P45 P44 P107 P110 P112 VDD XT1 VSS VSS CLKOUT P91 P94 P40 P42 P43
P100 P52 P50 P51 P101 P102 P103 P46 P47
Note
Connect the IC pin directly to VSS.
Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic LQFP. 2. Connect the D4 pin directly to VSS.
4
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN IDENTIFICATION
A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: HLDAK: HLDRQ: IC: INTP0 to INTP6: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: P70 to P77: P80 to P83: Address Bus Address/Data Bus AD Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog VDD Analog Reference Voltage Analog VSS Power Supply for Bus Interface Ground for Bus Interface Clock Output Data Strobe Hold Acknowledge Hold Request Internally Connected Interrupt Request From Peripherals Lower Byte Enable Non-maskable Interrupt Request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 P90 to P96: P100 to P107: P110 to P114: P120: RD: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK2: SCL
Note
Port 9 Port 10 Port 11 Port 12 Read Reset Real-time Port RTP Trigger Read/Write Status Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Input Timer Output Transmit Data Upper Byte Enable Power Supply Ground Wait Write Strobe High Level Data Write Strobe Low Level Data Crystal for Main Clock Crystal for Sub-clock
: :
SDA
Note
SI0 to SI2: SO0 to SO2: TI00, TI01, TI10, : TI11, TI2 to TI5 TO0 to TO5: TXD0, TXD1: UBEN: VDD: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2:
Note
Applies to the PD703014AY, 703015AY, and 703017AY only.
Data Sheet U14526EJ2V0DS00
5
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
INTERNAL BLOCK DIAGRAM
NMI INTP0 to INTP6 TI00, TI01, TI10, TI11 TO0, TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5
Mask ROM INTC PC Note 1 Timer/counters 16-bit timer: TM0, TM1 8-bit timer: TM2 to TM5 SIO
CPU Instruction queue
Multiplier 16 x 16 32
HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W/WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
32-bit barrel shifter RAM System registers
General registers 32 bits x 32
BCU ALU
Note 2
Note 3
SO0 SI0/SDANote 3 SCK0/SCLNote 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO2 SI2 SCK2 TXD1 RXD1 ASCK1
CSI0/I C
2
CSI1/UART0 CLKOUT X1 CG X2 XT1 (P114) XT2 RESET
Port CSI2
RTP
A/D converter
DMAC: 3 ch Watch timer Watchdog timer
RTP0 to RTP7 RTPTRG
AVDD AVREF AVSS ANI0 to ANI11 ADTRG
UART1
P120 P114 P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07
VDD VSS BVDD BVSS IC
Notes 1. PD703014A, 703014AY: 64 KB
PD703015A, 703015AY: 128 KB PD703017A, 703017AY: 256 KB
2. PD703014A, 703014AY, 703015A, 703015AY: 4 KB
PD703017A, 703017AY: 8 KB
3. Applies to the PD703014AY, 703015AY, and 703017AY only.
6
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
CONTENTS
1.
PIN FUNCTIONS.................................................................................................................................. 8
1.1 1.2 1.3 Port Pins..................................................................................................................................................... 8 Non-Port Pins........................................................................................................................................... 11 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14
2. 3. 4.
ELECTRICAL SPECIFICATIONS...................................................................................................... 18 PACKAGE DRAWINGS..................................................................................................................... 42 RECOMMENDED SOLDERING CONDITIONS ............................................................................... 44
Data Sheet U14526EJ2V0DS00
7
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1. PIN FUNCTIONS 1.1 Port Pins
(1/3)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 I/O Yes Port 3 8-bit I/O port Input/output can be specified in 1-bit units. I/O Yes Port 2 8-bit I/O port Input/output can be specified in 1-bit units. I/O Yes Port 1 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL Yes Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA SO0 SCK0/SCL SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2 SO2 SCK2 RXD1 TXD1 ASCK1 TI2/TO2 TI3/TO3 TI00 TI01 TI10 TI11 TO0/A13 TO1/A14 TI4/TO4/A15 TI5/TO5
Note Note
Note Applies to the PD703014AY, 703015AY, and 703017AY only. Remark PULL: On-chip pull-up resistor
8
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2/3)
Pin Name P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 Input No Port 8 4-bit input port Input No Port 7 8-bit input port I/O No Port 6 6-bit I/O port Input/output can be specified in 1-bit units. I/O No Port 5 8-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL No Function Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11
Remark
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
9
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(3/3)
Pin Name P90 P91 P92 P93 P94 P95 P96 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P114 P120 Input I/O No No Port 12 1-bit I/O port I/O Yes Port 11 5-bit I/O port Input/output can be specified in 1-bit units. P114 is fixed as input only. I/O Yes Port 10 8-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL No Function Port 9 7-bit I/O port Input/output can be specified in 1-bit units. Alternate Function LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP0/A5 RTP1/A6 RTP2/A7 RTP3/A8 RTP4/A9 RTP5/A10 RTP6/A11 RTP7/A12 A1 A2 A3 A4 XT1 WAIT
Remark
PULL: On-chip pull-up resistor
10
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1.2 Non-Port Pins
(1/3)
Pin Name A1 to A4 A5 to A12 I/O Output PULL Yes Function Low-order address bus used for external memory expansion Alternate Function P110 to P113 P100/RTP0 to P107/RTP7 P34/TO0 P35/TI1 P36/TI4/TO4 Output I/O No No High-order address bus used for external memory expansion 16-bit multiplexed address/data bus used for external memory expansion A/D converter external trigger input Analog input to A/D converter P60 to P65 P40 to P47 P50 to P57 P05/INTP4 P70 to P77 P80 to P83 Serial clock input for UART0 and UART1 P15/SCK1 P25 Output - Input - - - Output Output Output Input Input No - - - - - - No No No Yes External address strobe signal output Positive power supply for A/D converter Reference voltage input for A/D converter Ground potential for A/D converter Positive power supply for bus interface Ground potential for bus interface Internal system clock output External data strobe signal output Bus hold acknowledge output Bus hold request input External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination) P93/RD P95 P96 P01 to P04 P05/ADTRG P06/RTPTRG P07 Output Input Output Input Output No Yes No - Yes External data bus's low-order byte enable signal output Non-maskable interrupt request input Read strobe signal output System reset input Real-time output port P90/WRL P00 P93/DSTB - P100/A5 to P107/A12 P94 - - - - - -
A13 A14 A15 A16 to A21 AD0 to AD7 AD8 to AD15 ADTRG ANI0 to ANI7 ANI8 to ANI11 ASCK0 ASCK1 ASTB AVDD AVREF AVSS BVDD BVSS CLKOUT DSTB HLDAK HLDRQ INTP0 to INTP3 INTP4 INTP5 INTP6 LBEN NMI RD RESET RTP0 to RTP7 Input Input Input Input Yes No No Yes
Remark
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
11
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2/3)
Pin Name RTPTRG R/W RXD0 RXD1 SCK0 SCK1 SCK2 SCL SDA SI0 SI1 SI2 SO0 SO1 SO2 TI00 Input Yes External capture trigger input and external count clock input for TM0 External capture trigger input for TM0 External capture trigger input and external count clock input for TM1 External capture trigger input for TM1 External count clock input for TM2 External count clock input for TM3 External count clock input for TM4 External count clock input for TM5 Output Yes Pulse signal output for TM0 and TM1 Pulse signal output for TM2 Pulse signal output for TM3 Pulse signal output for TM4 Pulse signal output for TM5 Output Yes Serial transmit data output for UART0 and UART1 Output Yes Serial transmit data output (3-wire type) for CSI0 to CSI2 Input Yes I C serial clock I/O
2 2 Note
I/O Input Output Input
PULL Yes No Yes RTP external trigger input
Function
Alternate Function P06/INTP5 P92/WRH P13/SI1 P23
External read/write status output Serial receive data input for UART0 and UART1
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI2
P12 P15/ASCK0 P22 P12/SCK0
I C serial transmit/receive data I/O
Note
P10/SI0 P10 P13/RXD0 P20 P11 P14/TXD0 P21 P30
Serial receive data input (3-wire type) for CSI0 to CSI2
TI01 TI10
P31 P32
TI11 TI2 TI3 TI4 TI5 TO0, TO1 TO2 TO3 TO4 TO5 TXD0 TXD1 UBEN VDD VSS Output - - No - -
P33 P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5 P34/A13, P35/A14 P26/TI2 P27/TI3 P36/TI4/A15 P37/TI5 P14/SO1 P24
High-order byte enable signal output for external data bus Positive power supply pin Ground potential
P91 - -
Note Applies to the PD703014AY, 703015AY, and 703017AY only. Remark PULL: On-chip pull-up resistor
12
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(3/3)
Pin Name WAIT WRH I/O Input Output PULL No No Function Control signal input for inserting wait in bus cycle High-order byte write strobe signal output for external data bus Low-order byte write strobe signal output for external data bus Input - Input - - - Internally connected (connect directly to VSS) No Resonator connection for subsystem clock P114 - - No Resonator connection for main clock Alternate Function P120 P92/R/W
WRL X1 X2 XT1 XT2 IC
P90/LBEN - -
Remark
PULL: On-chip pull-up resistor
Data Sheet U14526EJ2V0DS00
13
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For the input/output schematic circuit diagram of each type, refer to Figure 1-1. Table 1-1. Types of Pin I/O Circuits (1/2)
Pin P00 P01 to P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26, P27 P30, P31 P32, P33 P34, P35 P36 P37 P40 to P47 P50 to P57 P60 to P65 P70 to P77 P80 to P83 NMI INTP0 to INTP3 Alternate Function I/O Circuit Type 8-A Recommended Connection of Unused Pins Input: Connect to VSS Output: Leave open
INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA SO0 SCK0/SCL SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2 SO2 SCK2 RXD1 TXD1 ASCK1 TI2/TO2, TI3/TO3 TI00, TI01 TI10, TI11 TO0/A13, TO1/A14 TI4/TO4/A15 TI5/TO5 AD0 to AD7 5 Input: Connect to BVDD or BVSS Output: Leave open 5-A 8-A
Note Note
10-A 26 10-A 8-A 26 10-A 8-A 26 10-A 8-A 5-A 8-A
Input: Connect to VDD or VSS Output: Leave open
AD8 to AD15
A16 to A21
ANI0 to ANI7
9
Connect to AVSS or AVDD
ANI8 to ANI11
Note Applies to the PD703014AY, 703015AY, and 703017AY only.
14
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin P90 P91 P92 P93 P94 P95 P96 P100 to P107 P110 to P113 P114 P120 Alternate Function LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP0/A5 to RTP7/A12 26 Input: Connect to VDD or VSS Output: Leave open I/O Circuit Type 5 Recommended Connection of Unused Pins Input: Connect to BVDD or BVSS Output: Leave open
A1 to A4
5-A
XT1 WAIT - - - - - -
16 5 - 4 2 - 16 - Input: Connect to BVDD or BVSS Output: Leave open Connect to AVSS Leave open - Leave open (when external clock is input to X1 pin) Leave open Always connect directly to VSS
AVREF CLKOUT RESET X2 XT2 IC
Data Sheet U14526EJ2V0DS00
15
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup enable Data
P-ch VDD P-ch IN/OUT
IN
Output disable Schmitt-triggered input with hysteresis characteristics Input enable Type 4 VDD Data P-ch OUT Output disable N-ch Pullup enable Data Type 8-A
N-ch
VDD
P-ch VDD P-ch IN/OUT
Output disable Push-pull output that can be set for high-impedance output (both P-ch and N-ch off)
N-ch
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Type 9
P-ch IN N-ch
+ -
Comparator
VREF (threshold voltage)
Input enable
Input enable
16
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 10-A
VDD
Type 26
VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Open drain Output disable
N-ch
Type 16 Feedback cut-off P-ch
XT1
XT2
Data Sheet U14526EJ2V0DS00
17
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Symbol VDD AVDD BVDD AVSS BVSS Input voltage VI1 VI2 Clock input voltage Analog input voltage Analog reference input voltage Output current, low VK VIAN AVREF IOL Note 1 Note 2 X1, XT1, VDD = 2.7 to 3.6 V Note 3 (AVDD) AVREF Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, P120, CLKOUT Total for P50 to P57, P60 to P65 Output current, high IOH Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, P120, CLKOUT Total for P50 to P57, P60 to P65 Output voltage VO1 VO2 Operating ambient temperature Storage temperature TA Tstg Note 1, VDD = 2.7 to 3.6 V Note 2, BVDD = 2.7 to 3.6 V Conditions Ratings -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +0.5 -0.5 to +0.5 -0.5 to VDD + 0.5
Note 4
Unit V V V V V V V V V V mA mA
-0.5 to BVDD + 0.5 -0.5 to VDD + 1.0
Note 4
Note 4
-0.5 to AVDD + 0.5 -0.5 to AVDD + 0.5 4.0 25
Note 4
Note 4
25
mA
25
mA
25 -4.0 -25
mA mA mA
-25
mA
-25
mA
-25 -0.5 to VDD + 0.5
Note 4
mA V V C C
-0.5 to BVDD + 0.5 -40 to +85 -65 to +150
Note 4
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins. 2. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins. 3. Ports 7, 8, and their alternate-function pins. 4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict.
18
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Operating Conditions
Internal Operation Clock Frequency 2 MHz fXX 17 MHz 2 MHz fXX 20 MHz fXT = 32.768 kHz Supply Voltage (VDD) 2.7 to 3.6 V 3.0 to 3.6 V 2.7 to 3.6 V Operating Ambient Temperature (TA) -40 to +85C -40 to +85C -40 to +85C
Data Sheet U14526EJ2V0DS00
19
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Recommended Oscillator (1) Main system clock oscillator (TA = -40 to +85C) (a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter Oscillation frequency
Symbol fXX
Conditions VDD = 2.7 to 3.6 V VDD = 3.0 to 3.6 V
MIN. 2 2
TYP.
MAX. 17 20
Unit MHz MHz s s
Oscillation stabilization time
Upon reset release Upon STOP mode release
2 /fXX Note
19
Note The TYP value differs depending on the setting of the oscillation stabilization time select register (OSTS). Caution Ensure that the duty of oscillation waveform is between 45% and 55%. Remarks 1. Connect the oscillator as close as possible to the X1 and X2 pins. 2. Do not route the wiring near broken lines. 3. Sufficiently evaluate the matching between the oscillator and resonator. (b) External clock input
X1
X2 Open
High-speed CMOS inverter External clock
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the X1 pin. 2. Sufficiently evaluate the matching between the PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY and the high-speed CMOS inverter.
20
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Subsystem clock oscillator (TA = -40 to +85C) (a) Connection of crystal resonator
XT1
XT2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXT
Conditions
MIN. 32
TYP. 32.768 10
MAX. 35
Unit kHz s
Remarks 1. Connect the oscillator as close as possible to the XT1 and XT2 pins. 2. Do not route the wiring near broken lines. 3. Sufficiently evaluate the matching between the oscillator and resonator. (b) External clock input
XT1
XT2
High-speed CMOS inverter
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin. 2. Sufficiently evaluate the matching between the PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY and the high-speed CMOS inverter.
Data Sheet U14526EJ2V0DS00
21
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
DC Characteristics (1) Operating conditions (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VOL2 Conditions Pins other than below Note 1 Note 2 X1, XT1 (P114), XT2 Pins other than below Note 1 Note 2 X1, XT1 (P114), XT2 Note 3 Note 4 Note 3 Note 4 (Except pins P10 and P12) VOL3 Input leakage current, high ILIH P10, P12 VI = VDD = AVDD = BVDD VI = 0 V IOL = 3 mA Pins other than below X1, XT1, XT2 Pins other than below X1, XT1, XT2 Output leakage current, high Output leakage current, low Supply current
Note 5
MIN. 0.7VDD 0.7AVDD 0.75VDD 0.8VDD VSS AVSS VSS VSS 0.8VDD 0.8VDD
TYP.
MAX. VDD AVDD VDD VDD 0.3VDD 0.3AVDD 0.2VDD 0.2VDD
Unit V V V V V V V V V V
IOH = -3 mA IOH = -1 mA IOL = 1.6 mA IOL = 1.6 mA
0.4 0.4
V V
0.4 5 20 -5 -20 5 -5
V
A A A A A A
mA
Input leakage current, low
ILIL
ILOH ILOL IDD1
VO = VDD = AVDD = BVDD VO = 0 V Normal operation fXX = 17 MHz All peripheral functions operating fXX = 17 MHz All peripheral functions operating fXX = 17 MHz Watch timer operating 17
30
IDD2
HALT mode
8
20
mA
IDD3 IDD4
IDLE mode
1 8
4 60
mA
STOP mode (subsystem oscillator, watch timer operating) STOP mode (subsystem oscillator stopped (XT1 = VSS))
A A
1
60
22
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(1) Operating conditions (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter Supply current
Note 5
Symbol IDD5
Conditions Subsystem clock normal operation mode fXT = 32.768 kHz (main system clock stopped) Subsystem clock IDLE mode fXT = 32.768 kHz (main system clock stopped, watch timer operating) VIN = 0 V
MIN.
TYP. 40
MAX. 140
Unit
A
IDD6
8
60
A
Pull-up resistance
RL
10
30
100
k
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins. 2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their alternate-function pins. 3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins. 4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternatefunction pins. 5. The TYP. value of VDD is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14526EJ2V0DS00
23
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Operating conditions (TA = -40 to +85C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VOL2 Conditions Pins other than below Note 1 Note 2 X1, XT1 (P114), XT2 Pins other than below Note 1 Note 2 X1, X2, XT1 (P114), XT2 Note 3 Note 4 Note 3 Note 4 (Except pins P10 and P12) VOL3 Input leakage current, high ILIH P10, P12 VI = VDD = AVDD = BVDD VI = 0 V IOL = 3 mA Pins other than below X1, XT1, XT2 Pins other than below X1, XT1, XT2 Output leakage current, high Output leakage current, low Supply current
Note 5
MIN. 0.7VDD 0.7AVDD 0.75VDD 0.8VDD VSS AVSS VSS VSS 0.8VDD 0.8VDD
TYP.
MAX. VDD AVDD VDD VDD 0.3VDD 0.3AVDD 0.2VDD 0.2VDD
Unit V V V V V V V V V V
IOH = -3 mA IOH = -1 mA IOL = 1.6 mA IOL = 1.6 mA
0.4 0.4
V V
0.4 5 20 -5 -20 5 -5
V
A A A A A A
mA
Input leakage current, low
ILIL
ILOH ILOL IDD1
VO = VDD VO = 0 V Normal operation HALT mode fXX = 20 MHz All peripheral functions operating fXX = 20 MHz All peripheral functions operating fXX = 20 MHz Watch timer operating 20
35
IDD2
9
22
mA
IDD3
IDLE mode
1.2
4.5
mA
IDD4
STOP mode (subsystem oscillator, watch timer operating) STOP mode (subsystem oscillator stopped (XT1 = VSS))
8 1
60 60
A A
24
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
(2) Operating conditions (TA = -40 to +85C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter Supply current
Note 5
Symbol IDD5
Conditions Subsystem clock normal operation mode fXT = 32.768 kHz (main system clock stopped) Subsystem clock IDLE mode fXT = 32.768 kHz (main system clock stopped, watch timer operating) VIN = 0 V
MIN.
TYP. 40
MAX. 140
Unit
A
IDD6
8
60
A
Pull-up resistance
RL
10
30
100
k
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins. 2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET and their alternate-function pins. 3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins. 4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternatefunction pins. 5. The TYP. value of VDD is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14526EJ2V0DS00
25
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage Symbol VDDDR IDDDR tRVD tFVD tHVD Conditions STOP mode VDDDR [V] 200 200 0 MIN. 1.8 1 TYP. MAX. 3.6 60 Unit V
A s s
ms
tDREL VIHDR VILDR All input ports All input ports
0 VIHn 0 VDDDR VILn
ms V V
Remarks 1. TYP. values are reference values for when TA = 25C. 2. n = 1 to 4
Setting STOP mode
tFVD
tRVD
VDD tHVD VDDDR tDREL
RESET (input)
VIHDR
NMI, INTP0 to INTP3 (input)
VIHDR
NMI, INTP0 to INTP3 (input) (when STOP mode is released at rising edge)
VILDR
Caution
Shifting to STOP mode and restoring from STOP mode must be performed at VDD = 2.7 V min. (fXX = 17 MHz) and VDD = 3.0 V min. (fXX = 20 MHz), respectively.
26
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
AC Characteristics AC Test Input Waveforms (1) P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, and their alternate-function pins
VDD
0.7VDD Test points 0.3VDD
0.7VDD 0.3VDD
0V
(2) P70 to P77, P80 to P83, and their alternate-function pins
AVDD
0.7AVDD Test points 0.3AVDD
0.7AVDD 0.3AVDD
0V
(3) P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their alternate-function pins
VDD
0.75VDD Test points 0.2VDD
0.75VDD 0.2VDD
0V
(4) X1, XT1 (P114), XT2
VDD
0.8VDD Test points 0.2VDD
0.8VDD 0.2VDD
0V
AC Test Output Test Points
0.8VDD Test points 0.4 V
0.8VDD 0.4 V
Data Sheet U14526EJ2V0DS00
27
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Load conditions
DUT (Device under test) CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
28
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Clock Timing (1) Operating conditions (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 input low-level width XT1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tXR tXF tCYK tWKH tWKL tKR tKF <4> <5> <6> <7> <8> <9> <10> 58.8 ns 0.4tCYK - 10 0.4tCYK - 10 10 10 tWXL <3> tWXH <2> Symbol tCYX <1> Conditions MIN. 58.8 28.5 26.4 12.8 26.4 12.8 0.5 (tCYX - tWXH - tWXL) 0.5 (tCYX - tWXH - tWXL) 31.2 s ns ns ns ns ns MAX. Unit ns
s
ns
s
ns
s
ns
Remarks 1. T = tCYK 2. Ensure that the duty is between 45% and 55%. (2) Operating conditions (TA = -40 to +85C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 input low-level width XT1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tXR tXF tCYK tWKH tWKL tKR tKF <4> <5> <6> <7> <8> <9> <10> 50.0 ns 0.4tCYK - 10 0.4tCYK - 10 10 10 tWXL <3> tWXH <2> Symbol tCYX <1> Conditions MIN. 50.0 28.5 22.5 12.8 22.5 12.8 0.5 (tCYX - tWXH - tWXL) 0.5 (tCYX - tWXH - tWXL) 31.2 s ns ns ns ns MAX. Unit ns
s
ns
s
ns
s
ns ns
Remarks 1. T = tCYK 2. Ensure that the duty is between 45% and 55%.
Data Sheet U14526EJ2V0DS00
29
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Clock Timing
<1> <2> <3>
X1, XT1 (input)
<4>
<5> <7>
<6> <8>
CLKOUT (output)
<9>
<10>
(1) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9 (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Output rise time Output fall time Symbol tOR tOF <11> <12> Conditions MIN. MAX. 20 20 Unit ns ns
(2) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9 (TA = -40 to +85C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Output rise time Output fall time Symbol tOR tOF <11> <12> Conditions MIN. MAX. 20 20 Unit ns ns
0.8VDD Output signal 0.4 V <12> 0.4 V <11>
0.8VDD
30
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Asynchronous) (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Bus output delay time from HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> <39> <40> 0.5T n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 15 0 (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 25 (1 + n)T - 25 (1 + n)T - 20 T - 15 1.5T - 25 (1.5 + n)T - 25 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 15 T - 15 15 Conditions MIN. 0.5T - 15 0.5T - 15 2 (2 + n)T - 25 (1 + n)T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after the read cycle (0 or 1). 4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
Data Sheet U14526EJ2V0DS00
31
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Synchronous) (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK Symbol tDKA tFKA <41> <42> Conditions MIN. 0 -12 MAX. 19 7 Unit ns ns
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF tDKHA
<43> <44> <45> <46> <47> <48> <49> <50> <51> <52> <53>
-12 -5 15 5
7 14
ns ns ns ns
19 15 5 15 5 19 19
ns ns ns ns ns ns ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
32
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output) <41> A16 to A21 (output), A1 to A15 (output), Note <16> <45> <42> AD0 to AD15 (I/O) Address <43> <14> <13> ASTB (output) <24> <44> <18> <15> <17> <44> <21> <20> <22> <23> <48> Hi-Z Data <43> <19> <46>
DSTB (output), RD (output) <32> <48> <34> <33> <35> <49> <49>
WAIT (input) <28> <30> <29> <31>
Note R/W (output), UBEN (output), LBEN (output) Remark WRL and WRH are high level.
Data Sheet U14526EJ2V0DS00
33
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output) <41> A16 to A21 (output), A1 to A15 (output), Note <47> AD0 to AD15 (I/O) Address <43> <13> <14> Data <43>
ASTB (output) <24> <44> <18> DSTB (output), WRL (output), WRH (output) <32> <48> <34> <33> <35> <49> <23> <48> <49> <25> <44> <26> <27> <21>
WAIT (input) <28> <30> <29> <31>
Note R/W (output), UBEN (output), LBEN (output) Remark RD is high level.
34
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Hold
TH CLKOUT (output) <50> <51>
TH
TH
TI
<50> <36>
HLDRQ (input)
<53> <39> <40>
<53>
HLDAK (output) <37> Hi-Z <38>
<52> A16 to A19 (output), Note
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), RD (output), WRL (output), WRH (output)
Hi-Z
Remark R/W (output), UBEN (output), LBEN (output)
Data Sheet U14526EJ2V0DS00
35
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Reset/Interrupt Timing (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter RESET high-level width RESET low-level width NMI high-level width NMI low-level width INTPn high-level width Symbol tWRSH tWRSL tWNIH tWNIL tWITH <54> <55> <56> <57> <58> n = 0 to 3 (analog noise elimination) n = 4 to 6 (digital noise elimination) INTPn low-level width tWITL <59> n = 0 to 3 (analog noise elimination) n = 4 to 6 (digital noise elimination) Conditions MIN. 500 500 500 500 500 3T + 20 500 3T + 20 MAX. Unit ns ns ns ns ns ns ns ns
Remark T = 1/fXX Reset
<54>
<55>
RESET (input)
Interrupt
<56>
<57>
NMI (input)
<58>
<59>
INTPn (input)
Remark n = 0 to 6
36
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
TIn Input Timing (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter TIn0, TIn1 high-level width TIn high-level width TIn0, TIn1 low-level width TIn low-level width tTILn <61> Symbol tTIHn <60> Conditions n = 0, 1 n = 2 to 5 n = 0, 1 n = 2 to 5 MIN. 2Tsam + 20 3T + 20 2Tsam + 20 3T + 20
Note Note
MAX.
Unit ns ns ns ns
Note Tsam (count clock cycle) can be selected from the following by setting the PRMn2 to PRMn0 bits of prescaler mode register n, n1 (PRMn, PRMn1). For n = 0 (TM0): Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTI cycle For n = 1 (TM1): Tsam = 2T, 4T, 16T, 32T, 128T, or 256T cycle However, when the TIn0 valid edge is selected as the count clock cycle, Tsam = 2T. Remark T = 1/fXX
<60>
<61>
Tln
Remark n = 00, 01, 10, 11, 2 to 5
Data Sheet U14526EJ2V0DS00
37
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
CSI Timing (1) Master mode (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter SCKn cycle time SCKn high-/low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 <62> <63> <64> <65> <66> Conditions MIN. 400 140 50 50 60 MAX. Unit ns ns ns ns ns
Remark n = 0 to 2 (2) Slave mode (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter SCKn cycle time SCKn high-/low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 <62> <63> <64> <65> <66> Conditions MIN. 400 140 50 50 60 MAX. Unit ns ns ns ns ns
Remark n = 0 to 2
<62> <63> SCKn (I/O) <63>
<64>
<65>
SIn (input)
Input data
<66>
SOn (output)
Output data
Remark n = 0 to 2
38
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
UART Timing (TA = -40 to +85C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol tKCY13 tKH13 tKL13 <67> <68> <69> Conditions MIN. 200 80 80 MAX. Unit ns ns ns
Remark n = 0, 1
<67> <68> <69>
ASCKn (input)
Remark n = 0 or 1
Data Sheet U14526EJ2V0DS00
39
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
I C Bus Mode (PD703014AY, 703015AY, 703017AY only)
2
(TA = -40 to +85C, VDD = 2.7 to 3.6 V, VSS = 0 V)
Parameter Symbol Normal Mode MIN. SCL clock frequency Bus-free time (between stop/start conditions) Hold time
Note 1
High-Speed Mode MIN. 0 1.3 MAX. 400 -
Unit
MAX. 100 -
fCLK tBUF <70>
0 4.7
kHz
s s s s s s
tHD:STA tLOW tHIGH tSU:STA
<71> <72> <73> <74>
4.0 4.7 4.0 4.7
- - - -
0.6 1.3 0.6 0.6
- - - -
SCL clock low-level width SCL clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time Capacitance load of each bus line
2
tHD:DAT
<75>
5.0
-
-
-
0 tSU:DAT tR <76> <77>
Note 2
- - 1000
0
Note 2
0.9
Note 3
s
ns ns
250 -
100
Note 4
-
Note 5
20 + 0.1Cb
300
tF
<78>
-
300
20 + 0.1Cb
Note 5
300
ns
tSU:STO Cb
<79>
4.0 -
- 400
0.6 -
- 400
s
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIHmin.. of SCL signal) in order to occupy the undefined area at the falling edge of SCL. 3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:
DAT)
needs to be satisfied.
2 2 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCL signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCL signal's low state hold time: Transmit the following data bit to the SDA line prior to the SCL line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF)
Remark The maximum operating frequency of the PD703014AY, 703015AY, and 703017AY is 17 MHz.
40
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
I C Bus Mode (PD703014AY, 703015AY, 703017AY only)
2
<72> SCL (I/O)
<73>
<78> <77> <71>
<75>
<76>
<74> <71> <79>
SDA (I/O) <70> Start Stop condition condition <77> <78> Restart condition Stop condition
A/D Converter (TA = -40 to +85C, VDD = AVDD = AVREF = 2.7 to 3.6 V, VSS = AVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Resolution Overall error
Note 1
Symbol
Conditions
MIN. 10
TYP. 10
MAX. 10 0.8
Unit bit %FSR
Conversion time Zero-scale error Full-scale error
Note 1
tCONV
5
100 0.4 0.4
s
%FSR %FSR LSB LSB V V
Note 1
Integral linearity error
Note 2
4 4 AVREF VIAN AIREF AIDD AVREF = AVDD 2.7 AVSS 360 1 3.6 AVREF 500 3
Differential linearity error
Note 2
Analog reference voltage Analog input voltage AVREF current Power supply current
A
mA
Notes 1. Excluding quantization error (0.05 %FSR) 2. Excluding quantization error (0.5 LSB) Remark LSB: Least Significant Bit FSR: Full Scale Range
Data Sheet U14526EJ2V0DS00
41
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
3. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
42
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
121-PIN PLASTIC FBGA (12x12)
E
w
SB
ZD
ZE
B
A D
13 12 11 10 9 8 7 6 5 4 3 2 1 NM L K J HG F E DC B A
INDEX MARK
w
SA
A y1 S A2 S
y
S
b
e
A1
x
M
S AB
ITEM D E w A A1 A2 e b x y y1 ZD ZE MILLIMETERS 12.000.10 12.000.10 0.20 1.480.10 0.350.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.20 1.20 P121F1-80-EA6
Data Sheet U14526EJ2V0DS00
43
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
4. RECOMMENDED SOLDERING CONDITIONS
The PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions (1) PD703014AGC-xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx PD703014AYGC-xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx PD703015AGC-xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx PD703015AYGC-xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx PD703017AGC-xxx xxx-8EU: 100-pin plastic LQFP (fine-pitch) (14 x 14) xxx PD703017AYGC-xxx
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
(2) PD703014AF1-xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx PD703014AYF1-xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx PD703015AF1-xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx PD703015AYF1-xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx PD703017AF1-xxx xxx-EA6: 121-pin plastic FBGA (12 x 12) xxx PD703017AYF1-xxx
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
44
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
[MEMO]
Data Sheet U14526EJ2V0DS00
45
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Caution
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
Reference document Note
Electrical Characteristics for Microcomputer (IEI-601)
Note
This document number is that of the Japanese version.
Related document PD70F3017A, 70F3017AY Data Sheet (U14527E) V850 Family and V850/SA1 are trademarks of NEC Corporation.
46
Data Sheet U14526EJ2V0DS00
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
J00.7
Data Sheet U14526EJ2V0DS00
47
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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